System and IC level analysis of electrostatic discharge (ESD) and electrical fast transient (EFT) immunity and associated coupling mechanisms

The exposure of electronic circuits to lightning, electrostatic discharge (ESD), electrical fast transients (EFT) or sine wave signals can reveal RF immunity problems. Typical problems include temporary malfunctions or permanent damage of integrated circuits (ICs). In an effort to reproduce those disturbances, a series of electromagnetic compatibility standards has been developed. However, a complete understanding of the root cause of the immunity problems has yet to be established. This dissertation discusses immunity problems in three papers, starting at the system level, via the coupling path into the IC --Abstract, page iv

ESD Susceptibility Characterization of an EUT by Using 3D ESD Scanning System

Electrostatic discharges (ESD) can lead to soft-errors (e.g., bit-errors, wrong resets etc.) in digital electronics. The use of lower threshold voltages and faster I/O increases the sensitivity. In the analysis of ESD problems, an exact knowledge of the affected pins and nets is essential for an optimal solution. In this paper, a three dimensional ESD scanning system which has been developed to record the ESD susceptibility map for printed circuit board is presented and the mechanisms that the ESD event couples into the digital devices is studied. The ESD susceptibility of a fast CMOS EUT is characterized by generating the susceptibility map of the EUT. A series of measurements of the noise coupled into a sensitive trace and pin during an ESD soft error event are presented

Experimental Investigation of the ESD Sensitivity of an 8-Bit Microcontroller

In this paper, the susceptibility of an 8-bit microcontroller to electrostatic discharge (ESD) and electrically fast transients was tested by injecting currents through a capacitive probe into the microcontroller package pins. The reaction of the microcontroller to discharges with different rise times and polarities were investigated by measuring the voltage on the tested pins and by observing the microcontroller\u27s clock output. Susceptibility varied significantly when injecting to one pin compared to another. Interestingly, the clock was more sensitive to currents injected into I/O pins than into pins directly related to the clock (e. g. EXTAL). Further work is underway to explain the causes of susceptibility inside the IC

Frequency-Domain Measurement Method for the Analysis of ESD Generators and Coupling

A method for analyzing electrostatic discharge (ESD) generators and coupling to equipment under test in the frequency domain is proposed. In ESD generators, the pulses are excited by the voltage collapse across relay contacts. The voltage collapse is replaced by one port of a vector network analyer (VNA). All the discrete and structural elements that form the ESD current pulse and the transient fields are excited by the VNA as if they were excited by the voltage collapse. In such a way, the method allows analyzing the current and field-driven linear coupling without having to discharge an ESD generator, eliminating the risk to the circuit and allowing the use of the wider dynamic range of a network analyzer relative to a real-time oscilloscope. The method is applicable to other voltage-collapse-driven tests, such as electrical fast transient, ultrawideband susceptibility testing but requires a linear coupling path

Advanced Full Wave ESD Generator Model for System Level Coupling Simulation

System level ESD tests can only be performed after hardware is available. Simulating the ESD coupling into a circuit allows at least parametric and quantitative studies of the expected ESD behavior. A complete simulation requires us to model the ESD generator, the passive elements of the DUT and the response of the ICs to injected noise. Having the ultimate objective of combining IC soft error response models with the DUT structure and the ESD generator we report on progresses in modeling the ESD generator and its coupling. The model improves the useful frequency range from a few hundred MHz to about 3 GHz

Correlation Between EUT Failure Levels and ESD Generator Parameters

Some system-level electrostatic discharge (ESD) tests repeat badly if different ESD generators are used. For improving repeatability, ESD generator specifications have been changed, and modified generators have been compared in a worldwide round robin test. The test showed up to 1 : 3 variations of failure levels. Multiple parameters that characterize ESD generators have been measured. This paper correlates the parameters to test result variations trying to distinguish between important and nonrelevant parameters. The transient fields show large variations among different ESD generators. A correlation has been observed in many equipment under tests (EUTs) between failure levels and the spectral content of the voltage induced in a semicircular loop. EUT resonance enhances the field coupling, and is the dominate failure mechanism. The regulation on the transient field is expected to improve the test repeatability

The Repeatability of System Level ESD Test and Relevant ESD Generator Parameters

Some system level ESD tests do not repeat well if different ESD generators are used. For improving the test repeatability, ESD generator specifications were considered to be changed and a world wide Round Robin test were performed in 2006 to compare the modified and unmodified ESD generators. The test results show the failure level variations up to 1:3 for an EUT among eight different ESD generators. Multiple ESD parameters including discharge currents and transient fields have been measured. This paper tries to find which parameters would predict the failure level the best in general. The transient fields show large variations among different ESD generators. The voltage induced in a semi-circular loop and the ringing after first discharge current peak show the best correlation to failure levels. The regulation on the transient field is expected to improve the test repeatability

Susceptibility Scanning as Failure Analysis Tool for System-Level Electrostatic Discharge (ESD) Problems

Susceptibility scanning is an increasingly adopted method for root cause analysis of system-level immunity sensitivities. It allows localizing affected nets and integrated circuits (ICs). Further, it can be used to compare the immunity of functionally identical or similar ICs or circuit boards. This paper explains the methodology as applied to electrostatic discharge and provides examples of scan maps and signals probed during immunity scanning. Limitations of present immunity analysis methods are discussed